1. Field of the Invention
The present invention relates to a semiconductor memory device, such as a flash memory or a DRAM, and a writing method of ID codes and upper addresses thereof, and in particular relates to a writing method of upper addresses in the case where a plurality of semiconductor elements are incorporated in a multi-chip package.
2. Description of the Related Art
For example, for a multi-chip package of a flash memory, each semiconductor chip needs to be assigned a different upper address. In order to arrange common wires for control pins and input/output pins of the semiconductor chips in the multi-chip package, the corresponding pins are all connected together. In this case, if each semiconductor chip isn't assigned an upper address, one-on-one selection for address input cannot be performed. Here, an upper address means the most significant address of an address range which is assigned differently from each semiconductor chip in a multi-chip package.
FIG. 1 is a sectional view showing the wire arrangement of semiconductor chips D1˜DN of a multi-chip package 10 in accordance with the conventional art. As shown in FIG. 1, a pin with the same name of each semiconductor chip is connected to a corresponding pin in the multi-chip package. Usually, to distinguish one semiconductor chip from the others, a chip enable (/CE) signal pin of each semiconductor chip (for example, /CE1,/ CE2, . . . /CEN) is bonded to a chip enable (CE) signal pin that is different from the other chip enable signal pins in the multi-chip package 10. However, in this case, (N−1) individual package pins are necessary in additionally. Note that in this specification, for a low active signal, “/” is added in front of the reference symbol of each signal instead of adding an over bar.
Furthermore, Patent document 1 discloses a semiconductor memory device having a plurality of semiconductor chips, wherein control signals are input from input/output pads and control pads connected together in order to separately activate a memory chip within a plurality of memory chips layered and connected together by a via hole. The semiconductor chip comprises a self-address memory portion storing a self chip address, a determination portion comparing a selection address input from the outside through the input/output pad with the self chip address and determining if there is consistency between them, and a control signal setting portion setting the control signal input to the self semiconductor chip into “active” or “inactive” according to the result of a consistency determination. However, the method still has big problems, including chip management, as will be described later.
Patent document 1: Japan Patent Application Publication No. 2008-077779
FIG. 2 is a circuit diagram showing a writing method for writing an ID code and an upper address to each of the semiconductor chips D1˜DN of the multi-chip package shown in FIG. 1. As shown in FIG. 2, the upper address is assigned by wire bonding a plurality of bonding pads of each semiconductor chip to a high-level voltage VCC lead frame or a low-level voltage VSS lead frame in, for example, the assembly process. After the upper address is assigned, each semiconductor chip can be selected appropriately by inputting an appropriate address. Here, the bonding pads occupy a huge area on the semiconductor chip, resulting in an increase of the semiconductor chip size.
In Patent document 1, the circuit is formed such that an upper address is written in each semiconductor chip before the assembly process and the address is compared with an input address. Therefore, special pads or bonding wires are not necessary. However, in the assembly process, more complicated control and chip management are required. In this regard, Patent document 1 cannot provide a flexible manufacturing method. When writing the upper address, it should be managed by chip location which address is assigned to which chip from the wafer test, and the respective chip written with the address should be picked up correctly for assembly. Such management is very difficult. Further, to write an address to a chip or to read the written address from the chip before the chip is picked up in the assembly process, each pad should be probed and provided with power or a signal. Therefore, the assembly process becomes more difficult than a pure assembly process, and manufacturing cost increases.
In order to solve the above problems, the purpose of the invention is to provide a semiconductor memory device and a writing method of ID codes and upper addresses thereof, capable of assigning and writing the ID codes and the upper addresses to each semiconductor chip in a multi-chip package, and not increasing the sizes of the semiconductor chips in comparison with the prior art.